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SiLago Documentation

Contributin to SiLago documentation

SiLago Documentation

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Software
Software
- Vesyla HLS
  Vesyla HLS
  - Tutorials
    
    Tutorials
    
    Getting Started
    
    Install Vesyla
    
    Run an example
  - How-to guides
    
    How-to guides
    
    How to map an application to SiLago
    
    Assemble a fabric
    
    Create a new component
    
    Write PASM Program
  - Explanations
    
    Explanations
    
    Architecture Overview
    
    CADFG
    
    Dependency Analysis
    
    Hazzard
    
    Scheduling
    
    IO
    
    Full System View
  - Reference
    
    Reference
    
    Scheduling Guide
    
    DRRA Components
    DRRA Components
    
    Instruction Set
    
    CMake Build System
- Sylva ALS
  Sylva ALS
  - Tutorials
    
    Tutorials
    
    Getting Started
  - How-to guides
    
    How-to guides
  - Explanations
    
    Explanations
    
    DSE
    DSE
    
    Binding
    
    Placing
    
    Routing
    
    NoC Synthesis
    
    GLIC Synthesis
    
    Simulation
    
    ASM
    ASM
    
    Memory Synthesis
    
    Re-routing
    
    NoC Resynthesis
  - Reference
    
    Reference
    
    Sylva Input Format
Hardware
Hardware
- Tutorials
  Tutorials
  - Getting Started
- How-to guides
  How-to guides
- Explanations
  Explanations
  - Architecture Overview
- Reference
  Reference
Contributing
Contributing
- Contribute to documentation
  Contribute to documentation
  - SiLago Docs Styleguide
  - MkDocs Usage
- Contribute to SiLago toolchain
  Contribute to SiLago toolchain
  - GitHub Contribution
    GitHub Contribution
    
    Vesyla
  - Code Styleguides
    
    Code Styleguides
    
    C++ Styleguide
    
    Rust Styleguide
- Contribute to SiLago hardware
  Contribute to SiLago hardware
  - VHDL Styleguide
  - SystemVerilog Styleguide
About
About
- About SiLago
- License

Contributin to SiLago documentation