Skip to content
SiLago Documentation
Fabric How-to guides
Search
silagokth
Home
Software
Hardware
Contributing
About
SiLago Documentation
silagokth
Home
Software
Software
Vesyla HLS
Vesyla HLS
Tutorials
Tutorials
Getting Started
Install Vesyla
Run an example
How-to guides
How-to guides
How to map an application to SiLago
Assemble a fabric
Create a new component
Write PASM Program
Explanations
Explanations
Architecture Overview
CADFG
Dependency Analysis
Hazzard
Scheduling
IO
Full System View
Reference
Reference
Scheduling Guide
DRRA Components
DRRA Components
Instruction Set
CMake Build System
Sylva ALS
Sylva ALS
Tutorials
Tutorials
Install Sylva
Getting Started
Run an example (LeNet-5)
How-to guides
How-to guides
Generate and run an example
Describe your own application
Provide an AlImp library
Tune the optimisation
Read the outputs and debug
Explanations
Explanations
Hardware Architecture
DSE
DSE
Binding
Placing
Routing
NoC Synthesis
GLIC Synthesis
Simulation
ASM
ASM
Memory Synthesis
Re-routing
NoC Resynthesis
TLB Code Generation
Transporter Code Generation
Control Synthesis
Reference
Reference
Sylva Input Format
Command-line Interface
Hardware Reference
Hardware
Hardware
Tutorials
Tutorials
Getting Started
How-to guides
How-to guides
Explanations
Explanations
Architecture Overview
Reference
Reference
Contributing
Contributing
Contribute to documentation
Contribute to documentation
SiLago Docs Styleguide
MkDocs Usage
Contribute to SiLago toolchain
Contribute to SiLago toolchain
GitHub Contribution
GitHub Contribution
Vesyla
Code Styleguides
Code Styleguides
C++ Styleguide
Rust Styleguide
Contribute to SiLago hardware
Contribute to SiLago hardware
VHDL Styleguide
SystemVerilog Styleguide
About
About
About SiLago
License
Fabric How-to guides
Back to top