Instruction Set (v2)
Warning
This is an old version of the instruction set. Please refer to Instruction Set (v3) for the latest version.
Instructions
Note
Instruction fields marked by bold font are controllable and observable. Users can modify these fields in Manas input file.
HALT
| Field | Position | Width | Default Value | Description |
|---|---|---|---|---|
| instr_code | [26, 23] | 4 | 0 | Instruction code for HALT |
REFI
| Field | Position | Width | Default Value | Description |
|---|---|---|---|---|
| instr_code | [80, 77] | 4 | 1 | Instruction code for REFI |
| port_no | [76, 75] | 2 | 0 | Selects one of the RFile port. [0]:w0; [1]:w1; [2]:r0; [3]:r1; |
| extra | [74, 73] | 2 | 0 | How many following chunks? |
| init_addr_sd | [72, 72] | 1 | 0 | Is init_addr static or dymamic? [0]:s; [1]:d; |
| init_addr | [71, 66] | 6 | 0 | Initial address. |
| l1_iter | [65, 60] | 6 | 0 | Level-1 iteration - 1. |
| init_delay | [59, 54] | 6 | 0 | Initial delay. |
| l1_iter_sd | [53, 53] | 1 | 0 | Is level-1 iteration static or dymamic? [0]:s; [1]:d; |
| init_delay_sd | [52, 52] | 1 | 0 | Is initial delay static or dynamic? [0]:s; [1]:d; |
| unused_0 | [51, 50] | 2 | 2 | Deprecated. |
| l1_step_sd | [49, 49] | 1 | 0 | Is level-1 step static or dynamic? [0]:s; [1]:d; |
| l1_step | [48, 43] | 6 | 1 | Level-1 step |
| l1_step_sign | [42, 42] | 1 | 0 | The sign of level-1 step. [0]:+; [1]:-; |
| l1_delay_sd | [41, 41] | 1 | 0 | Is the level-1 delay static or dynamic? [0]:s; [1]:d; |
| l1_delay | [40, 37] | 4 | 0 | The level-1 delay, middle delay |
| l2_iter_sd | [36, 36] | 1 | 0 | Is level-2 iteration static or dymamic? [0]:s; [1]:d; |
| l2_iter | [35, 31] | 5 | 0 | The level-2 iteration - 1. |
| l2_step | [30, 27] | 4 | 1 | The level-2 step. |
| unused_1 | [26, 23] | 4 | 3 | Deprecated. |
| l2_delay_sd | [22, 22] | 1 | 0 | Is the level-2 delay static or dynamic? [0]:s; [1]:d; |
| l2_delay | [21, 16] | 6 | 0 | The level-2 delay, repetition delay. |
| unused_2 | [15, 10] | 6 | 0 | Deprecated. |
| l1_delay_ext | [9, 8] | 2 | 0 | The extened bits near MSB of l1_delay. |
| l2_iter_ext | [7, 7] | 1 | 0 | The extened bits near MSB of l2_iter. |
| l2_step_ext | [6, 5] | 2 | 0 | The extened bits near MSB of l2_step. |
| unused_3 | [4, 2] | 3 | 0 | Deprecated. |
| dimarch | [1, 1] | 1 | 0 | Is reading/writing from/to DiMArch? [0]:n; [1]:y; |
| compress | [0, 0] | 1 | 0 | Is the data compressed? [0]:n; [1]:y; |
DPU
| Field | Position | Width | Default Value | Description |
|---|---|---|---|---|
| instr_code | [26, 23] | 4 | 4 | Instruction code for DPU |
| mode | [22, 18] | 5 | 0 | The DPU mode. [0]:idle; [1]:add; [2]:sum_acc; [3]:add_const; [4]:subt; [5]:subt_abs; [6]:mode_6; [7]:mult; [8]:mult_add; [9]:mult_const; [10]:mac; [11]:ld_ir; [12]:axpy; [13]:max_min_acc; [14]:max_min_const; [15]:mode_15; [16]:max_min; [17]:shift_l; [18]:shift_r; [19]:sigm; [20]:tanhyp; [21]:expon; [22]:lk_relu; [23]:relu; [24]:div; [25]:acc_softmax; [26]:div_softmax; [27]:ld_acc; [28]:scale_dw; [29]:scale_up; [30]:mac_inter; [31]:mode_31; |
| control | [17, 16] | 2 | 2 | The controll mode: saturation and operator type. [0]:nosat_int; [1]:nosat_fx; [2]:sat_int; [3]:sat_fx; |
| unused_0 | [15, 10] | 6 | 2 | Deprecated. |
| acc_clear | [9, 2] | 8 | 0 | The accumulator clear signal will be triggered if the accumulation reaches this number. It also serves as immediate value for some DPU mode. |
| io_change | [1, 0] | 2 | 0 | The IO mode: negate input and absolute output. [0]:no_change; [1]:negate_in0; [2]:negate_in1; [3]:abs_out; |
SWB
| Field | Position | Width | Default Value | Description |
|---|---|---|---|---|
| instr_code | [26, 23] | 4 | 5 | Instruction code for SWB |
| unused0 | [22, 22] | 1 | 1 | Deprecated. |
| src_row | [21, 21] | 1 | 0 | Source row. |
| src_block | [20, 20] | 1 | 0 | Source block, RF or DPU. [0]:rf; [1]:dpu; |
| src_port | [19, 19] | 1 | 0 | source port. |
| hb_index | [18, 16] | 3 | 0 | Index of horizontal bus. This is the column difference of the src and dest cell shifting by 2. For example if the path is from [0,0] to [1,2], the column difference is -2, so the hb_index = -2+2=0. |
| send_to_other_row | [15, 15] | 1 | 0 | Flag of whether src and dest row are equal. [0]:n; [1]:y; |
| v_index | [14, 12] | 3 | 0 | Index of vertical bus. This is the dest port. If destination is RF, the v_index is the port number, if the dest is DPU, the v_index is port number + 2. |
JUMP
| Field | Position | Width | Default Value | Description |
|---|---|---|---|---|
| instr_code | [26, 23] | 4 | 6 | Instruction code for JUMP |
| pc | [22, 17] | 6 | 0 | The PC to jump to |
WAIT
| Field | Position | Width | Default Value | Description |
|---|---|---|---|---|
| instr_code | [26, 23] | 4 | 7 | Instruction code for WAIT |
| cycle_sd | [22, 22] | 1 | 0 | Is the cycle static or dynamic? [0]:s; [1]:d; |
| cycle | [21, 7] | 15 | 0 | Number of cycles - 1 |
LOOP
| Field | Position | Width | Default Value | Description |
|---|---|---|---|---|
| instr_code | [53, 50] | 4 | 8 | Instruction code for LOOP |
| extra | [49, 49] | 1 | 0 | How many following chunks? |
| loopid | [48, 47] | 2 | 0 | The id of the loop manager slot. |
| endpc | [46, 41] | 6 | 0 | The PC where loop ends. |
| start_sd | [40, 40] | 1 | 0 | Is the start static or dynamic? [0]:s; [1]:d; |
| start | [39, 34] | 6 | 0 | The start of iterator. |
| iter_sd | [33, 33] | 1 | 0 | Is the iteration count static or dynamic? [0]:s; [1]:d; |
| iter | [32, 27] | 6 | 0 | The number of iteration. |
| step_sd | [26, 26] | 1 | 0 | Is the step static or dynamic? [0]:s; [1]:d; |
| step | [25, 20] | 6 | 1 | The iteration step. |
| link | [19, 16] | 4 | 0 | The loops that have the same endpc will be linked together. This field is 1-hot encoded. |
BW
| Field | Position | Width | Default Value | Description |
|---|---|---|---|---|
| instr_code | [26, 23] | 4 | 9 | Instruction code for BW |
| config | [22, 21] | 2 | 0 | Bitwidth configuration for DPU: 4-bit, 8-bit, 16-bit |
RACCU
| Field | Position | Width | Default Value | Description |
|---|---|---|---|---|
| instr_code | [26, 23] | 4 | 10 | Instruction code for RACCU |
| mode | [22, 20] | 3 | 0 | RACCU mode [0]:idle; [1]:add; [2]:sub; [3]:shift_r; [4]:shift_l; [5]:mult; [6]:mult_add; [7]:mult_sub; |
| operand1_sd | [19, 19] | 1 | 0 | Is the first operand static or dynamic? [0]:s; [1]:d; |
| operand1 | [18, 12] | 7 | 0 | First operand. |
| operand2_sd | [11, 11] | 1 | 0 | Is the second operand static or dynamic? [0]:s; [1]:d; |
| operand2 | [10, 4] | 7 | 0 | Second operand. |
| result | [3, 0] | 4 | 0 | The RACCU register to store the result. |
BRANCH
| Field | Position | Width | Default Value | Description |
|---|---|---|---|---|
| instr_code | [26, 23] | 4 | 11 | Instruction code for BRANCH |
| mode | [22, 21] | 2 | 0 | The branch mode |
| false_pc | [20, 15] | 6 | 0 | The PC to jump to in case the condition is false. |
ROUTE
| Field | Position | Width | Default Value | Description |
|---|---|---|---|---|
| instr_code | [26, 23] | 4 | 12 | Instruction code for ROUTE |
| horizontal_dir | [22, 22] | 1 | 0 | The horizontal direction: West or East. [0]:w; [1]:e; |
| horizontal_hops | [21, 19] | 3 | 0 | The horizontal hops. |
| vertical_dir | [18, 18] | 1 | 0 | The vertical direction: South or North. [0]:s; [1]:n; |
| vertical_hops | [17, 15] | 3 | 0 | The vertical hops. |
| direction | [14, 14] | 1 | 0 | The data transfer direction: Read or Write. [0]:r; [1]:w; |
| select_drra_row | [13, 13] | 1 | 0 | The drra row that send/recieve the data. |
SRAM
| Field | Position | Width | Default Value | Description |
|---|---|---|---|---|
| instr_code | [80, 77] | 4 | 13 | Instruction code for SRAM |
| rw | [76, 76] | 1 | 0 | Read or Write [0]:r; [1]:w; |
| init_addr | [75, 69] | 7 | 0 | Initial address |
| init_delay | [68, 65] | 4 | 0 | initial delay |
| l1_iter | [64, 58] | 7 | 0 | level-1 iteration - 1. |
| l1_step | [57, 50] | 8 | 1 | level-1 step |
| l1_delay | [49, 44] | 6 | 0 | level-1 delay |
| l2_iter | [43, 37] | 7 | 0 | level-2 iteration - 1. |
| l2_step | [36, 29] | 8 | 1 | level-2 step |
| l2_delay | [28, 23] | 6 | 0 | level-2 delay |
| init_addr_sd | [22, 22] | 1 | 0 | Is initial address static or dynamic? [0]:s; [1]:d; |
| l1_iter_sd | [21, 21] | 1 | 0 | Is level-1 iteration static or dynamic? [0]:s; [1]:d; |
| l2_iter_sd | [20, 20] | 1 | 0 | Is level-2 iteration static or dynamic? [0]:s; [1]:d; |
| init_delay_sd | [19, 19] | 1 | 0 | Is initial delay static or dynamic? [0]:s; [1]:d; |
| l1_delay_sd | [18, 18] | 1 | 0 | Is level-1 delay static or dynamic? [0]:s; [1]:d; |
| l2_delay_sd | [17, 17] | 1 | 0 | Is level-2 delay static or dynamic? [0]:s; [1]:d; |
| l1_step_sd | [16, 16] | 1 | 0 | Is level-1 step static or dynamic? [0]:s; [1]:d; |
| l2_step_sd | [15, 15] | 1 | 0 | Is level-2 step static or dynamic? [0]:s; [1]:d; |
| hops | [14, 11] | 4 | 0 | Number of hops to reach the DiMArch cell - 1 |
ISA Description File
JSON Schema
The ISA description file uses json format and validated by the following json schema:
{
"type": "object",
"properties": {
"platform": { "type": "string" },
"instr_bitwidth": { "type": "integer" },
"instr_code_bitwidth": { "type": "integer" },
"instruction_templates": {
"type": "array",
"items": {
"type": "object",
"properties": {
"code": { "type": "integer" },
"name": { "type": "string" },
"phase": { "type": "integer" },
"max_chunk": { "type": "integer" },
"segment_templates": {
"type": "array",
"items": {
"type": "object",
"properties": {
"name": { "type": "string" },
"bitwidth": { "type": "integer" },
"default_val": { "type": "integer" },
"controllable": { "type": "boolean" },
"observable": { "type": "boolean" },
"verbo_map": {
"type": "array",
"items": {
"type": "object",
"properties": {
"key": { "type": "integer" },
"val": { "type": "string" }
}
}
},
"comment": { "type": "string" }
},
"required": ["name", "bitwidth", "comment"]
},
"uniqueItems": true
}
},
"required": ["code", "name"]
},
"uniqueItems": true
}
},
"required": [
"platform",
"instr_bitwidth",
"instr_code_bitwidth",
"instruction_templates"
]
}
Note
You can validate a ISA description json file using this schema on Json Schema Validator.
JSON
The ISA description file used for DRRA is shown as follow:
{
"platform": "SiLago 1",
"instr_bitwidth": 27,
"instr_code_bitwidth": 4,
"instruction_templates": [
{
"code": 0,
"name": "HALT",
"phase": 1,
"max_chunk": 1,
"segment_templates": []
},
{
"code": 1,
"name": "REFI",
"phase": 4,
"max_chunk": 3,
"segment_templates": [
{
"name": "port_no",
"comment": "Selects one of the RFile port.",
"bitwidth": 2,
"verbo_map": [
{ "key": 0, "val": "w0" },
{ "key": 1, "val": "w1" },
{ "key": 2, "val": "r0" },
{ "key": 3, "val": "r1" }
]
},
{
"name": "extra",
"comment": "How many following chunks?",
"bitwidth": 2
},
{
"name": "init_addr_sd",
"comment": "Is init_addr static or dymamic?",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "init_addr",
"comment": "Initial address.",
"bitwidth": 6
},
{
"name": "l1_iter",
"comment": "Level-1 iteration - 1.",
"bitwidth": 6
},
{
"name": "init_delay",
"comment": "Initial delay.",
"bitwidth": 6,
"controllable": true
},
{
"name": "l1_iter_sd",
"comment": "Is level-1 iteration static or dymamic?",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "init_delay_sd",
"comment": "Is initial delay static or dynamic?",
"bitwidth": 1,
"controllable": true,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "unused_0",
"comment": "Deprecated.",
"bitwidth": 2,
"default_val": 2,
"controllable": false,
"observable": false
},
{
"name": "l1_step_sd",
"comment": "Is level-1 step static or dynamic?",
"bitwidth": 1,
"default_val": 0,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "l1_step",
"comment": "Level-1 step",
"bitwidth": 6,
"default_val": 1
},
{
"name": "l1_step_sign",
"comment": "The sign of level-1 step.",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "+" },
{ "key": 1, "val": "-" }
]
},
{
"name": "l1_delay_sd",
"comment": "Is the level-1 delay static or dynamic?",
"bitwidth": 1,
"controllable": true,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "l1_delay",
"comment": "The level-1 delay, middle delay",
"bitwidth": 4,
"controllable": true
},
{
"name": "l2_iter_sd",
"comment": "Is level-2 iteration static or dymamic?",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "l2_iter",
"comment": "The level-2 iteration - 1.",
"bitwidth": 5
},
{
"name": "l2_step",
"comment": "The level-2 step.",
"bitwidth": 4,
"default_val": 1
},
{
"name": "unused_1",
"comment": "Deprecated.",
"bitwidth": 4,
"default_val": 3,
"controllable": false,
"observable": false
},
{
"name": "l2_delay_sd",
"comment": "Is the level-2 delay static or dynamic?",
"bitwidth": 1,
"controllable": true,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "l2_delay",
"comment": "The level-2 delay, repetition delay.",
"bitwidth": 6,
"controllable": true
},
{
"name": "unused_2",
"comment": "Deprecated.",
"bitwidth": 6,
"default_val": 0,
"controllable": false,
"observable": false
},
{
"name": "l1_delay_ext",
"comment": "The extened bits near MSB of l1_delay.",
"controllable": true,
"bitwidth": 2
},
{
"name": "l2_iter_ext",
"comment": "The extened bits near MSB of l2_iter.",
"bitwidth": 1
},
{
"name": "l2_step_ext",
"comment": "The extened bits near MSB of l2_step.",
"bitwidth": 2
},
{
"name": "unused_3",
"comment": "Deprecated.",
"bitwidth": 3,
"default_val": 0,
"controllable": false,
"observable": false
},
{
"name": "dimarch",
"comment": "Is reading/writing from/to DiMArch?",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "n" },
{ "key": 1, "val": "y" }
]
},
{
"name": "compress",
"comment": "Is the data compressed?",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "n" },
{ "key": 1, "val": "y" }
]
}
]
},
{
"code": 4,
"name": "DPU",
"phase": 4,
"max_chunk": 1,
"segment_templates": [
{
"name": "mode",
"comment": "The DPU mode.",
"bitwidth": 5,
"verbo_map": [
{ "key": 0, "val": "idle" },
{ "key": 1, "val": "add" },
{ "key": 2, "val": "sum_acc" },
{ "key": 3, "val": "add_const" },
{ "key": 4, "val": "subt" },
{ "key": 5, "val": "subt_abs" },
{ "key": 6, "val": "mode_6" },
{ "key": 7, "val": "mult" },
{ "key": 8, "val": "mult_add" },
{ "key": 9, "val": "mult_const" },
{ "key": 10, "val": "mac" },
{ "key": 11, "val": "ld_ir" },
{ "key": 12, "val": "axpy" },
{ "key": 13, "val": "max_min_acc" },
{ "key": 14, "val": "max_min_const" },
{ "key": 15, "val": "mode_15" },
{ "key": 16, "val": "max_min" },
{ "key": 17, "val": "shift_l" },
{ "key": 18, "val": "shift_r" },
{ "key": 19, "val": "sigm" },
{ "key": 20, "val": "tanhyp" },
{ "key": 21, "val": "expon" },
{ "key": 22, "val": "lk_relu" },
{ "key": 23, "val": "relu" },
{ "key": 24, "val": "div" },
{ "key": 25, "val": "acc_softmax" },
{ "key": 26, "val": "div_softmax" },
{ "key": 27, "val": "ld_acc" },
{ "key": 28, "val": "scale_dw" },
{ "key": 29, "val": "scale_up" },
{ "key": 30, "val": "mac_inter" },
{ "key": 31, "val": "mode_31" }
]
},
{
"name": "control",
"comment": "The controll mode: saturation and operator type.",
"bitwidth": 2,
"default_val": 2,
"verbo_map": [
{ "key": 0, "val": "nosat_int" },
{ "key": 1, "val": "nosat_fx" },
{ "key": 2, "val": "sat_int" },
{ "key": 3, "val": "sat_fx" }
]
},
{
"name": "unused_0",
"comment": "Deprecated.",
"bitwidth": 6,
"default_val": 2,
"controllable": false,
"observable": false
},
{
"name": "acc_clear",
"comment": "The accumulator clear signal will be triggered if the accumulation reaches this number. It also serves as immediate value for some DPU mode.",
"bitwidth": 8
},
{
"id": 4,
"name": "io_change",
"comment": "The IO mode: negate input and absolute output.",
"bitwidth": 2,
"verbo_map": [
{ "key": 0, "val": "no_change" },
{ "key": 1, "val": "negate_in0" },
{ "key": 2, "val": "negate_in1" },
{ "key": 3, "val": "abs_out" }
]
}
]
},
{
"code": 5,
"name": "SWB",
"phase": 3,
"max_chunk": 1,
"segment_templates": [
{
"name": "unused0",
"comment": "Deprecated.",
"bitwidth": 1,
"default_val": 1,
"controllable": false,
"observable": false
},
{
"name": "src_row",
"comment": "Source row.",
"bitwidth": 1
},
{
"name": "src_block",
"comment": "Source block, RF or DPU.",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "rf" },
{ "key": 1, "val": "dpu" }
]
},
{
"name": "src_port",
"comment": "source port.",
"bitwidth": 1
},
{
"name": "hb_index",
"comment": "Index of horizontal bus. This is the column difference of the src and dest cell shifting by 2. For example if the path is from [0,0] to [1,2], the column difference is -2, so the hb_index = -2+2=0.",
"bitwidth": 3
},
{
"name": "send_to_other_row",
"comment": "Flag of whether src and dest row are equal.",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "n" },
{ "key": 1, "val": "y" }
]
},
{
"name": "v_index",
"comment": "Index of vertical bus. This is the dest port. If destination is RF, the v_index is the port number, if the dest is DPU, the v_index is port number + 2.",
"bitwidth": 3
}
]
},
{
"code": 6,
"name": "JUMP",
"phase": 1,
"max_chunk": 1,
"segment_templates": [
{
"name": "pc",
"comment": "The PC to jump to",
"bitwidth": 6
}
]
},
{
"code": 7,
"name": "WAIT",
"phase": 2,
"max_chunk": 1,
"segment_templates": [
{
"name": "cycle_sd",
"comment": "Is the cycle static or dynamic?",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "cycle",
"comment": "Number of cycles - 1",
"bitwidth": 15
}
]
},
{
"code": 8,
"name": "LOOP",
"phase": 1,
"max_chunk": 2,
"segment_templates": [
{
"name": "extra",
"comment": "How many following chunks?",
"bitwidth": 1
},
{
"name": "loopid",
"comment": "The id of the loop manager slot.",
"bitwidth": 2
},
{
"name": "endpc",
"comment": "The PC where loop ends.",
"bitwidth": 6
},
{
"name": "start_sd",
"comment": "Is the start static or dynamic?",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "start",
"comment": "The start of iterator.",
"bitwidth": 6
},
{
"name": "iter_sd",
"comment": "Is the iteration count static or dynamic?",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "iter",
"comment": "The number of iteration.",
"bitwidth": 6
},
{
"name": "step_sd",
"comment": "Is the step static or dynamic?",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "step",
"comment": "The iteration step.",
"bitwidth": 6,
"default_val": 1
},
{
"name": "link",
"comment": "The loops that have the same endpc will be linked together. This field is 1-hot encoded.",
"bitwidth": 4,
"controllable": false
}
]
},
{
"code": 9,
"name": "BW",
"phase": 1,
"max_chunk": 1,
"segment_templates": [
{
"name": "config",
"comment": "Bitwidth configuration for DPU: 4-bit, 8-bit, 16-bit",
"bitwidth": 2
}
]
},
{
"code": 10,
"name": "RACCU",
"phase": 2,
"max_chunk": 1,
"segment_templates": [
{
"name": "mode",
"comment": "RACCU mode",
"bitwidth": 3,
"verbo_map": [
{ "key": 0, "val": "idle" },
{ "key": 1, "val": "add" },
{ "key": 2, "val": "sub" },
{ "key": 3, "val": "shift_r" },
{ "key": 4, "val": "shift_l" },
{ "key": 5, "val": "mult" },
{ "key": 6, "val": "mult_add" },
{ "key": 7, "val": "mult_sub" }
]
},
{
"name": "operand1_sd",
"comment": "Is the first operand static or dynamic?",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "operand1",
"comment": "First operand.",
"bitwidth": 7
},
{
"name": "operand2_sd",
"comment": "Is the second operand static or dynamic?",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "operand2",
"comment": "Second operand.",
"bitwidth": 7
},
{
"name": "result",
"comment": "The RACCU register to store the result.",
"bitwidth": 4
}
]
},
{
"code": 11,
"name": "BRANCH",
"phase": 1,
"max_chunk": 1,
"segment_templates": [
{
"name": "mode",
"comment": "The branch mode",
"bitwidth": 2
},
{
"name": "false_pc",
"comment": "The PC to jump to in case the condition is false.",
"bitwidth": 6
}
]
},
{
"code": 12,
"name": "ROUTE",
"phase": 4,
"max_chunk": 1,
"segment_templates": [
{
"name": "horizontal_dir",
"comment": "The horizontal direction: West or East.",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "w" },
{ "key": 1, "val": "e" }
]
},
{
"name": "horizontal_hops",
"comment": "The horizontal hops.",
"bitwidth": 3
},
{
"name": "vertical_dir",
"comment": "The vertical direction: South or North.",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "n" }
]
},
{
"name": "vertical_hops",
"comment": "The vertical hops.",
"bitwidth": 3
},
{
"name": "direction",
"comment": "The data transfer direction: Read or Write.",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "r" },
{ "key": 1, "val": "w" }
]
},
{
"name": "select_drra_row",
"comment": "The drra row that send/recieve the data.",
"bitwidth": 1
}
]
},
{
"code": 13,
"name": "SRAM",
"phase": 5,
"max_chunk": 3,
"segment_templates": [
{
"name": "rw",
"comment": "Read or Write",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "r" },
{ "key": 1, "val": "w" }
]
},
{
"name": "init_addr",
"comment": "Initial address",
"bitwidth": 7
},
{
"name": "init_delay",
"comment": "initial delay",
"bitwidth": 4,
"controllable": true
},
{
"name": "l1_iter",
"comment": "level-1 iteration - 1.",
"bitwidth": 7
},
{
"name": "l1_step",
"comment": "level-1 step",
"bitwidth": 8,
"default_val": 1
},
{
"name": "l1_delay",
"comment": "level-1 delay",
"bitwidth": 6,
"controllable": true
},
{
"name": "l2_iter",
"comment": "level-2 iteration - 1.",
"bitwidth": 7
},
{
"name": "l2_step",
"comment": "level-2 step",
"bitwidth": 8,
"default_val": 1
},
{
"name": "l2_delay",
"comment": "level-2 delay",
"bitwidth": 6,
"controllable": true
},
{
"name": "init_addr_sd",
"comment": "Is initial address static or dynamic?",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "l1_iter_sd",
"comment": "Is level-1 iteration static or dynamic?",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "l2_iter_sd",
"comment": "Is level-2 iteration static or dynamic?",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "init_delay_sd",
"comment": "Is initial delay static or dynamic?",
"bitwidth": 1,
"controllable": true,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "l1_delay_sd",
"comment": "Is level-1 delay static or dynamic?",
"bitwidth": 1,
"controllable": true,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "l2_delay_sd",
"comment": "Is level-2 delay static or dynamic?",
"bitwidth": 1,
"controllable": true,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "l1_step_sd",
"comment": "Is level-1 step static or dynamic?",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "l2_step_sd",
"comment": "Is level-2 step static or dynamic?",
"bitwidth": 1,
"verbo_map": [
{ "key": 0, "val": "s" },
{ "key": 1, "val": "d" }
]
},
{
"name": "hops",
"comment": "Number of hops to reach the DiMArch cell - 1",
"bitwidth": 4
}
]
}
]
}